6502 Altair Design

The Basics:

The basic architecture is to be a bus-based 6502 system with a front panel that permits the user to set any valid address and read or write from memory. Expansion will be through cards connected to the system's buses using a 2x25 pin header with a pinout compatible with the Planck 6502 design.

Initial Features

1. 2x 32K SRAM

2. Simple address decoding to select either SRAM chip, no I/O or expansion capability

3. LEDs display status of all address and data bus lines

4. SPDT switches buffered and gated to address and data bus lines

5. Hold switch to stop processor

6. Clock step switch (produces one clock cycle)

7. Instruction step switch (enables clock for one instruction cycle using SYNC)

8. Reset switch

9. Debouncing on all switch inputs (filter/latch/etc)

Chip Selection:

I can get original 6502 or 65C02 chips. That is what Keith intends to use. I believe I will purchase WS65C02S chips from Western Design Center. They have several advantages over many of the other 6500 variants but there are two things that matter to me most. First, they are fully static designs. They can be halted and resumed without losing state. Second, they have a bus enable pin to release the address bus and put the CPU pins in a high-Z state. This will make connecting 16 switches to the address lines a lot simpler since I won't need a bunch of logic gates to disconnect the CPU.

Future Expansion:

• Variable clock- possibly 1Hz-10MHz or something like that. Digital control maybe?

• Arduino/RP2040 boostrap expansion board (will copy a selected program to RAM and reset the 6502)

• "debug" supervisor to monitor address lines and do "things" at setpoints (halt, print status, trigger interrupts, etc) 

• HEX address and data bus display

• HEX keypad

• LCD screen

• USB keyboard input via RP2040 (ie: Raspberry Pi Pico or similar)

• RS-232 via 6850/6551 ACIA

• VIA/PIA/RIOT/etc- there were many support chips for the 6800 and 6502. Whatever is available and I have interest in might get added

• FPGA (or possibly PLCC) address decoder (Keith is currently looking at this)